Clik here to view.
New Materials Solve Key 3D NAND Issue
At the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide,...
View ArticleClik here to view.
New Book: Vertical 3D Memory Technologies
Wiley has recently published a new book by Betty Prince titled Vertical 3D NAND Technologies that is one to consider if you want to bring yourself up to speed on recent research behind today’s and...
View ArticleClik here to view.
Samsung Begins Operations at its Xi’an Fab
Samsung has announced that the company’s newest memory fabrication plant (Fab) in Xi’an, China has “begun full-scale production operations”, adding that: “The new facility will manufacture Samsung’s...
View ArticleClik here to view.
3D NAND: Who Will Make It and When?
This series has looked at 3D NAND technology in a good deal of technical depth. The last question to be answered centers around the players and the timing of the technology. A lot has been said about...
View ArticleClik here to view.
3D NAND’s Impact on the Equipment Market
A very unusual side effect of the move to 3D NAND will be the impact on the equipment market. 3D NAND takes the pressure off of lithographic steps and focuses more attention on deposition and etch....
View ArticleClik here to view.
How Do You Erase and Program 3D NAND?
Some of my readers have asked: “How is 3D NAND programmed and erased? Is it any different from planar NAND?” In a word: No. (Before I get too far into this allow me to admit that The Memory Guy...
View ArticleClik here to view.
3D NAND: Benefits of Charge Traps over Floating Gates
A prior post in this series (3D NAND: Making a Vertical String) discussed the difficulties of successfully manufacturing a charge trap flash bit. Still, Spansion, and now other flash makers, have...
View ArticleClik here to view.
3D NAND: How do You Access the Control Gates?
One of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array....
View ArticleClik here to view.
What is a 3D NAND?
In the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not be scaled much farther in length and width on the die’s surface. Toshiba invented a 3D NAND...
View ArticleClik here to view.
Why Do We Need 3D NAND?
A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be....
View ArticleClik here to view.
New Materials Solve Key 3D NAND Issue
At the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide,...
View ArticleClik here to view.
New Book: Vertical 3D Memory Technologies
Wiley has recently published a new book by Betty Prince titled Vertical 3D NAND Technologies that is one to consider if you want to bring yourself up to speed on recent research behind today’s and...
View ArticleClik here to view.
Samsung Begins Operations at its Xi’an Fab
Samsung has announced that the company’s newest memory fabrication plant (Fab) in Xi’an, China has “begun full-scale production operations”, adding that: “The new facility will manufacture Samsung’s...
View ArticleClik here to view.
3D NAND: Who Will Make It and When?
This series has looked at 3D NAND technology in a good deal of technical depth. The last question to be answered centers around the players and the timing of the technology. A lot has been said about...
View ArticleClik here to view.
3D NAND’s Impact on the Equipment Market
A very unusual side effect of the move to 3D NAND will be the impact on the equipment market. 3D NAND takes the pressure off of lithographic steps and focuses more attention on deposition and etch....
View ArticleClik here to view.
How Do You Erase and Program 3D NAND?
Some of my readers have asked: “How is 3D NAND programmed and erased? Is it any different from planar NAND?” In a word: No. (Before I get too far into this allow me to admit that The Memory Guy...
View ArticleClik here to view.
3D NAND: Benefits of Charge Traps over Floating Gates
A prior post in this series (3D NAND: Making a Vertical String) discussed the difficulties of successfully manufacturing a charge trap flash bit. Still, Spansion, and now other flash makers, have...
View ArticleClik here to view.
3D NAND: How do You Access the Control Gates?
One of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array....
View ArticleClik here to view.
What is a 3D NAND?
In the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not be scaled much farther in length and width on the die’s surface. Toshiba invented a 3D NAND...
View ArticleClik here to view.
Why Do We Need 3D NAND?
A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be....
View Article
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