At the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material. This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.
For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.
imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.” Further they report that on-state current (ION) and transconductance (gm) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation. The device’s characteristics are shown in this post’s graphic.
The consortium reports that the current through the poly-Si channel in existing 3D NAND designs decreases in proportion to the number of memory layers, rendering it unsatisfactory for long-term scaling. The channel current decreases because the polysilicon’s conduction is impaired by scattering at the boundaries of polysilicon’s random-sized gains, an issue that doesn’t exist with the monocrystalline silicon used to make planar NAND flash. A thorough discussion of the problem can be found in Andrew Walker’s fine 3DInCites posts on polysilicon channel issues.
Interestingly, the new material has been proven to work with holes as small as 45nm, which is about half the diameter of the ~80nm channel hole in Samsung’s current 3D NAND chips. Hole diameters limit 3D NAND’s ability to use lithographic scaling.
Although the addition of new materials presents new challenges, the use of III-V materials in the channel is one step toward allowing 3D NAND to scale beyond its current 48-layer level. The Memory Guy would like to remind readers, however, that there are many other issues that must be resolved before 3D NAND can become cost competitive with today’s planar chips. These will be the subject of an upcoming post.
